`timescale 1ps/1ps

module inv_1 ( X, A );
  output X;
  input A;
  
  assign X = ~A;
endmodule

module buf_1 ( X, A );
  output X;
  input A;
  
  buf U1 (X, A);
endmodule

module inv_2 ( X, A );
  output X;
  input A;
  
  assign X = ~A;
endmodule

module buf_2 ( X, A );
  output X;
  input A;
  
  buf U1 (X, A);
endmodule

module inv_4 ( X, A );
  output X;
  input A;
  
  assign X = ~A;
endmodule

module buf_4 ( X, A );
  output X;
  input A;
  
  buf U1 (X, A);
endmodule
























































//100











































































































































//240









//250

